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Cache memory
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#	Item
761	VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks Leonidas Kontothanassisy, Galen Hunt, Robert Stets, Nikolaos Hardavellas, Michał Cierniak, Srinivasan Parthasarathy, Wagner Meira, Jr., Sandhya Dwarka Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2003-02-22 02:32:06 Distributed computing architecture Computer memory Cache coherency Distributed shared memory CPU cache Scalability Shared memory Speedup Concurrent data structure Computing Concurrent computing Parallel computing
762	Improving Application Performance by Dynamically Trading Frequency for Complexity in a GALS Microprocessor∗ Greg Semeraro, David H. Albonesi, Steven Dropsho, Grigorios Magklis, and Michael L. Scott URCS Technical Repor Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-02-12 17:49:46 Cache Computing CPU cache Computer memory Microprocessors Alpha 21264 Microarchitecture Branch predictor R8000 Computer hardware Computer architecture Central processing unit
763	VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks1 Leonidas Kontothanassis2 , Galen Hunt, Robert Stets, Nikolaos Hardavellas, Michał Cierniak, Srinivasan Parthasarathy, Wagner Meira, Jr., Sandhya Dwar Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-31 21:35:13 Computer architecture Parallel computing Computer memory Distributed shared memory CPU cache Cache Cell Shared memory Scalability Computing Concurrent computing Distributed computing architecture
764	A Framework for Using Processor Cache as RAM (CAR) Eswaramoorthi Nallusamy University of New Mexico October 10, 2005 Add to Reading List Source URL: coreboot.org Language: English - Date: 2007-04-03 20:28:37 Computer memory Cache CPU cache Central processing unit MESI protocol Memory type range register Cache algorithms MSI protocol Cache coherency Computing Computer hardware
765	Dvi to PostScript converter, Version 2.0 of November 28, 1988 Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 18:37:58 Parallel computing Computer memory Central processing unit Cache Non-Uniform Memory Access CPU cache Shared memory Microarchitecture Memory virtualization Computing Concurrent computing Computer hardware
766	COVER FEATURE Dynamically Tuning Processor Resources with Adaptive Processing Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-01-03 18:19:54 Cache Computing CPU cache Computer memory Cell Computer architecture Central processing unit Computer hardware
767	Nonblocking Transactions Without Indirection Using Alert-on-Update ∗ Michael F. Spear, Arrvindh Shriraman, Luke Dalessandro, Sandhya Dwarkadas, and Michael L. Scott Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2007-03-22 21:05:08 Computing Data Software transactional memory CPU cache Linearizability Lock Database Extensible Storage Engine Redo log Transaction processing Data management Concurrency control
768	Tech. Rep[removed]Software Cache Coherence for Large Scale Multiprocessors Leonidas I. Kontothanassis and Michael L. Scott Department of Computer Science University of Rochester Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 22:55:06 Cache coherency Parallel computing Computer memory Central processing unit Cache coherence CPU cache Shared memory Cache Distributed shared memory Computing Concurrent computing Computer architecture
769	Computer Architecture News, Sept. 1995, pp[removed]Efficient Shared Memory with Minimal Hardware Support Leonidas I. Kontothanassis and Michael L. Scott Department of Computer Science University of Rochester Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 19:43:02 Computer memory Non-Uniform Memory Access Cache coherence Distributed shared memory CPU cache Shared memory False sharing Memory architecture Cache Computing Concurrent computing Parallel computing
770	Fourth Workshop on Scalable Shared Memory Multiprocessors, Chicago, IL, April 1994 Scalable Atomic Primitives for Distributed Shared Memory Multiprocessors (Extended Abstract) Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 18:54:48 Concurrency Compare-and-swap Linearizability Non-blocking algorithm Test-and-set Load-link/store-conditional CPU cache Parallel computing Transactional memory Concurrency control Computing Computer architecture

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